The present invention relates to an error correcting and controlling system. More particularly, in a data transmission system in which an error correcting code is added to data to automatically correct random t-bit errors (t .gtoreq. 2) and detect (t+1)-bit errors, the invention relates to an error correcting and controlling system comprising a memory for storing error bit positions indicated by a syndrome at address positions corresponding one-to-one to the outputs of said syndrome, wherein stored contents of said memory are read out and correction and detection of errors are performed based on the read-out contents.
In a data transmission system such as a main memory device of a data processing system, there has heretofore been adopted a method using a so-called SEC/DED Hamming code, in which automatic correction of 1-bit errors and detection of 2-bit errors are performed. With the recent improvement of the degree of integration in integrated circit (IC) memory elements, it has been desired to adopt an error correcting code capable of automatic correction of errors of t-bits (t .gtoreq. 2) and detection of errors of (t+1)-bits.
As an error correcting code of the desired type, there is known a so-called BCH code. This code and conventional coding methods are detailed in, for example, Miyagawa et al, "Theory of Coding" (published by SHOKODO).
In general, in an error correction control system, code words are produced by adding check bits to information bits on the basis of the above-mentioned code logic, and when using information, syndromes are produced from said code words consisting of the information bits and the check bits added to the information bits. From these syndromes, the number of errors, if any, is known, as well as the position of bits in error or "error bits". Check bits are generated from the information bits through a specified logic circuit (i.e. a check bit generating circuit), according to the above-mentioned code logic. Syndrome signals are also produced from the information bits and check bits through a predetermined syndrome producing circuit.
In one conventional example, the syndrome signals are decoded by the logic circuit so as to determine the existance or no-existance of errors, the number of errors, and the positions of the error bits. In other examples, a shift register is used. However, in a case where errors of more than two bits are to be corrected, there are the disadvantages in that, in the case of the former example, the logic circuits become enormous in number and complicated, and in the case of the other examples (employing shift registers), a long time is required for the processing.